1. Technical Field of the Invention
The invention relates to semiconductor processing, and more particularly to the formation of integrated circuit structures having CMOS devices protected from radiation and/or hot electrons by a patterned nitride passivation layer formed over the integrated circuit structure.
2. Background of the Invention
Much of today's high-density integrated circuitry has been made possible by small-geometry CMOS (Complementary Metal Oxide Semiconductor) technology, well known to those skilled in the art of semiconductor processing. Most modem microprocessors and large-scale integrated circuits are made using small-geometry CMOS processes (2 micron line widths and below).
CMOS technology is particularly desirable in military and aerospace applications because of its high noise immunity and low power consumption. However, military and aerospace environments tend to be characterized by high levels of radiation, particularly electron and proton radiation,and standard CMOS circuits are known to have some problems with high-radiation environments. While it is possible to construct radiation shields for CMOS military applications, this tends to add weight, expense, and complexity; requires extensive testing; and negates much of the desirability of CMOS for these application.
Also well known to those skilled in the art is that CMOS technology is typified by logic gates constructed from complementary pairs of MOS Field Effect Transistors (FET's) (p-channel nd n-channel) in a sort of a push-pull configuration where only one transistor of any given pair is "on" at a time, such that CMOS gates (ideally) draw no steady-state current. The inputs to CMOS gates, being the unloaded gates of insulated-gate FET's (MOS transistors are also known as insulated-gate field effect transistors, or IGFETs, by virtue of an insulating layer of SiO.sub.2 between the gate and the active channel area of the transistor), draw no steady-state current either. The only currents drawn by CMOS circuitry are due to leakages and to switching currents, which result from the charging and discharging of parasitic capacitances at the time of a logic state change.
"Radiation hardness" refers to the ability of a semiconductor device to withstand radiation without alteration of its electrical characteristics. A semiconductor devices is said to be radiation hardened (rad-hard), radiation tolerant, or radiation resistant if it can continue to function within specifications after exposure to a specified amount of radiation. Semiconductor devices can be damaged or destroyed by the effects of nuclear radiation from natural and man-made sources. Radiation changes the electrical properties of solid state devices, leading to possible failure of any system incorporating them.
Electrons and protons have proven to be the most harmful forms of radiation in terms of their effect on CMOS semiconductor devices. Rad-hard devices and circuits have been developed to minimize the effects of these forces. The devices can be designed to be rad-hard, or the normal manufacturing process can be modified to produce rad-hard devices with special isolation techniques. Radiation hardening now permits systems designers to take advantage of the benefits of CMOS technology in high-performance, high-reliability products intended for application where radiation is present.
Ionization is the principal agent that damages or destroys CMOS devices. It is caused by photon (gamma or X-ray) interactions, fast neutron interactions, and charged (alpha and beta) particles.
As the dose of ionizing radiation increases, the number of carders generated in silicon will increase. Out in space it might take many years for a device to absorb high levels of radiation. For example,it might take 20 years for an IC (integrated circuit) to absorb a total does of 100,000 rads (Si). However, in the presence of a nuclear explosion, a device might reach this total dose within hundreds of nanoseconds. This type of pulse photon exposure is referred to as (extreme) transient radiation.
Particularly troublesome to CMOS devices in high radiation environments are active parasitic devices which occur within the CMOS devices themselves, particularly field isolation MOS ("field transistor", or "parasitic field transistor"; used interchangeably herein) and parasitic SCR (silicon controlled rectifier) structures. These structures are well known to those skilled in the art of semiconductor processing. NMOS (the n-channel part of the complementary pairs of transistors in CMOS structures) field transistor leakage and parasitic SCR latch-up are known to cause fatal (unrecoverable) misoperation of CMOS designs in high radiation environments. NMOS field transistor leakage is known to be induced by large negative threshold shifts in parasitic field transistor as a cumulative effect of radiation. This effect, being cumulative, permanently destroys the usefulness of CMOS devices over time as a function of the total dose of radiation received by the CMOS devices. (Numerous prior-art techniques are available for dealing with parasitic SCR structures, and are beyond the scope of this specification.)
Numerous radiation tolerant (rad-hard) designs of CMOS devices have been proposed and implemented. Typically, these designs are significantly larger and/or slower than their conventional CMOS counterparts. Since the NMOS transistors in CMOS structures are particularly sensitive to radiation effects, particularly field inversion in parasitic transistors, many techniques are aimed primarily at protecting only the NMOS transistor by such methods as building guard structures or guard rings into the n-channel devices which adjust the threshold of the parasitic transistors. Examples of such techniques for creating rad-hard CMOS devices and the characterization thereof are given in H. Hatano and Satoru Takasuka, "Total Dos Radiation-Hardened Latch-up Free CMOS Structures for Radiation-Tolerant VLSI Designs", IEEE Trans. Nucl. Sci., Vol. NS-33, No. 6, 1986; and in commonly-owned, co-pending patent application Ser. No. 07/911,861; entitled "RADIATION HARDENED CMOS STRUCTURE USING AN IMPLANTED P GUARD AND METHOD FOR THE MANUFACTURE THEREOF", filed Jul. 10, 1992, by Owens et al.
These "guard" techniques provide significant improvement in total-dose radiation hardness, but can often require significantly more space than is required for their non-radiation-hard counterparts, and may increase the risk of N +/P- junction breakdown.
Other techniques which may be used to improve total-dose radiation hardness include:
(1) Change the size of the island mask (used to control the size of the N+ source and drain diffusion "islands") to increase the spacing to the N+ diffusion. This technique has the disadvantage of dramatically increasing the size of the transistor, reducing overall circuit density, and is only partially effective. PA1 (2) Perform a blanket P- implant to adjust parasitic field transistor thresholds. This technique reduces field leakage, but increases parasitic capacitances (reducing the speed of the transistor), does not act as an additional field guard ring (increase risk of field inversion), and increases the risk of N+/P- junction breakdown. PA1 (3) Use a nitride passivation layer. This technique reduces field leakage, but increase CMOS threshold shifts (changes active characteristics of CMOS circuits), limiting total dose radiation tolerance. PA1 (4) Photo-implant a guard structure such as that described in commonly-owned co-pending U.S. patent application Ser. No. 07/911,861, filed Jul. 10, 1992, by Owens et al. This technique provides good overall characteristics, but increases the risk of N+ P- junction breakdown, increases the transistor size slightly, and may be difficult, if not impossible to implement when smaller sub-micron geometries are employed.
As a final processing step, a passivation layer, typically nitride or oxide (or some combination thereof), is usually applied to CMOS integrated circuitry, which is then etched to expose the bond pads areas below. This passivation layer provides a moisture barrier, acts as an ion "getter" for contaminants and, in general, protects the integrated circuit against the outside environment during the assembly process.
Another effect known to cause negative threshold shifts in small-geometry n-channel devices is caused by high-energy electrons (hot-electrons) which occur as a natural result of operating small-geometry n-channel devices at high electric fields (e.g., greater than 10.sup.4 volts/centimeter). These hot-electrons behave similarly to ionizing radiation and cause threshold shifts by much the same mechanism, but come from within the device rather than an external source.
It has been observed that nitride passivation reduces n-channel field leakage during total-dose radiation, and is an excellent moisture barrier, but has two troubling side-effects. Nitride passivation can cause CMOS threshold shifts due to a trapped charge phenomenon resulting from "silicon dangling bonds". As a result of this phenomenon, interface states are generated that increase the resulting CMOS device's sensitivity to smaller total radiation doses and hot electron degradation. This "silicon dangling bond" effect occurs as a result of the interaction of photon radiation and/or hot electrons with Si--H (silicon-hydrogen) bonds, which Si--H bonds occur as a natural result of nitride passivation. While the nitride passivation protects the n-channel transistors against radiation, this trapped charge effect increases threshold shifts of the p-channel devices, thereby contributing to field-edge leakage. Conversely, the hot electrons adversely impact the n-channel transistors protected by nitride passivation.
Oxide passivation, on the other hand, gives considerably lower CMOS threshold shifts and improves hot electron immunity. However, it does not protect the n-channel devices from radiation-induced field leakage and is not as good a moisture barrier as nitride.
While neither oxide nor nitride passivation provides the combination of characteristics required for high total-dose radiation-hard CMOS circuitry, the concept of using a passivation layer or layers to protect CMOS devices against radiation and hot electron degradation is particularly attractive, since it requires virtually no additional circuit area, does not appreciably slow the circuitry, and is relatively simple process.
The techniques of the prior art described hereinabove have been discussed with respect to CMOS devices, however, the problems of the prior apply equally to any semiconductor technology which incorporates MOS devices, including mixed technologies (e.g., bipolar and MOS transistors on the same semiconductor die).